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[IEEE 2014 IEEE 23rd Asian Test Symposium (ATS) - Hangzhou, China (2014.11.16-2014.11.19)] 2014 IEEE 23rd Asian Test Symposium - FPGA-Based Subset Sum Delay Lines
Wang, Chung-Yun, Chen, Yu-Yi, Huang, Jiun-Lang, Huang, Xuan-LunYear:
2014
Language:
english
DOI:
10.1109/ATS.2014.60
File:
PDF, 313 KB
english, 2014