TOP: an algorithm for three-level combinational logic...

IEE Proceedings - Circuits Devices and Systems 2004 Vol. 151; Iss. 4

TOP: an algorithm for three-level combinational logic optimisation

Dubrova, E., Ellervee, P., Miller, D.M., Muzio, J.C., Sullivan, A.J.
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Volume:
151
Year:
2004
Language:
english
Journal:
IEE Proceedings - Circuits, Devices and Systems
DOI:
10.1049/ip-cds:20040159
File:
PDF, 286 KB
english, 2004
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