A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

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IEEE Journal of Solid-State Circuits 2015

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Szortyka, Viki, Shi, Qixian, Raczkowski, Kuba, Parvais, Bertrand, Kuijk, Maarten, Wambacq, Piet
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Year:
2015
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2015.2442998
File:
PDF, 2.51 MB
english, 2015
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