FALPEM: Framework for Architectural-Level Power Estimation...

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015 / 7 Vol. 34; Iss. 7

FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems

Chhabra, Amit, Rawat, Harsh, Jain, Mohit, Tessier, Pascal, Pierredon, Daniel, Bergher, Laurent, Kumar, Promod
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Volume:
34
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/TCAD.2014.2387859
Date:
July, 2015
File:
PDF, 882 KB
english, 2015
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