![](/img/cover-not-exists.png)
Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files
Liang, Zhibin, Zhang, Wei, Ma, Yung-ChengVolume:
11
Language:
english
Journal:
ACM Transactions on Architecture and Code Optimization
DOI:
10.1145/2632218
Date:
July, 2014
File:
PDF, 2.32 MB
english, 2014