Cross-layer reliability evaluation, moving from the...

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Microprocessors and Microsystems 2015 / 6

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview

Vallero, A., Tselonis, S., Foutris, N., Kaliorakis, M., Kooli, M., Savino, A., Politano, G., Bosio, A., Di Natale, G., Gizopoulos, D., Di Carlo, S.
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Language:
english
Journal:
Microprocessors and Microsystems
DOI:
10.1016/j.micpro.2015.06.003
Date:
June, 2015
File:
PDF, 1.46 MB
english, 2015
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