An instruction timing model of CPU performance

ACM SIGARCH Computer Architecture News 1977 / 03 Vol. 5; Iss. 7

An instruction timing model of CPU performance

Peuto, Bernard L., Shustek, Leonard J.
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Volume:
5
Language:
english
Journal:
ACM SIGARCH Computer Architecture News
DOI:
10.1145/633615.810667
Date:
March, 1977
File:
PDF, 1.20 MB
english, 1977
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