Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors with Partially Elevated Source/Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies
Sugihara, Kohei, Miura, Naruhisa, Furukawa, Taisuke, Nakahata, Takumi, Nishioka, Yasutaka, Yamakawa, Satoshi, Abe, Yuji, Maruno, Shigemitsu, Tokuda, YasunoriVolume:
39
Language:
english
Journal:
Japanese Journal of Applied Physics
DOI:
10.1143/JJAP.39.387
Date:
February, 2000
File:
PDF, 657 KB
english, 2000