Whitespace-Aware TSV Arrangement in 3-D Clock Tree...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 / 9 Vol. 23; Iss. 9

Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis

Liu, Wulong, Wang, Yu, Chen, Guoqing, Ma, Yuchun, Xie, Yuan, Yang, Huazhong
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Volume:
23
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2014.2354347
Date:
September, 2015
File:
PDF, 3.68 MB
english, 2015
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