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Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic
R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. J. Hollander, T. Clark, K. Wang, J. H. Kim, D. Gundlach, K. P. Cheung, J. Suehle, R. Engel-herbert, S. Stemmer, S. DattaYear:
2015
Language:
english
DOI:
10.1109/VLSIT.2015.7223676
File:
PDF, 1.21 MB
english, 2015