A 10-bit 300-MS/s asynchronous SAR ADC with strategy of...

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A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65nm CMOS

Y. Liang, Z. Zhu, R. Ding
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Year:
2015
Language:
english
DOI:
10.1016/j.mejo.2015.08.008
File:
PDF, 1.95 MB
english, 2015
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