![](/img/cover-not-exists.png)
An Additional 12% Power Reduction in Practical Digital Chips with a Low-Power Design Using Post-Fabrication Clock-Timing Adjustment
Susa, Tatsuya, Murakawa, Masahiro, Takahashi, Eiichi, Furuya, Tatsumi, Higuchi, Tetsuya, Furuichi, Shinji, Ueda, Yoshitaka, Wada, AtsushiVolume:
48
Language:
english
Journal:
Japanese Journal of Applied Physics
DOI:
10.1143/JJAP.48.04C076
Date:
April, 2009
File:
PDF, 533 KB
english, 2009