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[IEEE Proceedings of 39th Design Automation Conference - New Orleans, LA, USA (2002.6.10-2002.6.14)] Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) - Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients
Badaroglu, M., Tiri, K., Donnay, S., Wambacq, P., Verbauwhede, I., Gielen, G., De Man, H.Year:
2002
Language:
english
DOI:
10.1109/DAC.2002.1012658
File:
PDF, 845 KB
english, 2002