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[IEEE 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Boston, MA, USA (2015.7.8-2015.7.10)] Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15) - An architecture-level cache simulation framework supporting advanced PMA STT-MRAM
Wu, Bi, Cheng, Yuanqing, Wang, Ying, Todri-Sanial, Aida, Sun, Guangyu, Torres, Lionel, Zhao, WeishengYear:
2015
Language:
english
DOI:
10.1109/NANOARCH.2015.7180576
File:
PDF, 160 KB
english, 2015