Conduction barrier offset engineering for DRAM capacitor...

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Solid-State Electronics 2015 / 9

Conduction barrier offset engineering for DRAM capacitor scaling

Pešić, Milan, Knebel, Steve, Cho, Kyuho, Jung, Changhwa, Chang, Jaewan, Lim, Hanjin, Kolomiiets, Nadiia, Afanas’ev, Valeri V., Mikolajick, Thomas, Schroeder, Uwe
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Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2015.08.012
Date:
September, 2015
File:
PDF, 1.48 MB
english, 2015
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