[IEEE 2015 19th International Symposium on VLSI Design and Test (VDAT) - Ahmedabad, India (2015.6.26-2015.6.29)] 2015 19th International Symposium on VLSI Design and Test - Timing model for two stage buffer and its application in ECSM characterization
Chaurasiya, Yogesh, Bhargava, Surabhi, Sharma, Arvind, Kaur, Baljit, Anand, BulusuYear:
2015
Language:
english
DOI:
10.1109/ISVDAT.2015.7208075
File:
PDF, 568 KB
english, 2015