Spur reducing architecture of frequency synthesiser using switched capacitors
Mandal, Debashis, Bhattacharyya, Tarun Kanti, Mandal, PradipVolume:
8
Language:
english
Journal:
IET Circuits, Devices & Systems
DOI:
10.1049/iet-cds.2013.0200
Date:
July, 2014
File:
PDF, 1.21 MB
english, 2014