Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer
Ho, Weng-Geng, Chang, Joseph Sylvester, Chong, Kwen-Siong, Gwee, Bah-HweeVolume:
9
Language:
english
Journal:
IET Circuits, Devices & Systems
DOI:
10.1049/iet-cds.2014.0103
Date:
July, 2015
File:
PDF, 890 KB
english, 2015