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SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 23 February 2014)] Design-Process-Technology Co-optimization for Manufacturability VIII - Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM
Sturtevant, John L., Capodieci, Luigi, Vandewalle, Boris, Chava, Bharani, Sakhare, Sushil, Ryckaert, Julien, Dusa, MirceaVolume:
9053
Year:
2014
Language:
english
DOI:
10.1117/12.2048079
File:
PDF, 1.65 MB
english, 2014