A Reduced-sp-\(\hbox {D3L}_{\mathrm{sum}}\)Adder-Based High Frequency\(4\times 4\)Bit Multiplier Using Dadda Algorithm
Shabbir, Zain, Ghumman, Anas Razzaq, Chaudhry, Shabbir MajeedVolume:
35
Language:
english
Journal:
Circuits, Systems, and Signal Processing
DOI:
10.1007/s00034-015-0201-7
Date:
September, 2016
File:
PDF, 3.60 MB
english, 2016