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Solid-State Electronics 2015 / 12

Low voltage logic circuits exploiting gate level dynamic body biasing in 28nm UTBB FD-SOI

Taco, Ramiro, Levi, Itamar, Lanuzza, Marco, Fish, Alexander
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Language:
english
Journal:
Solid-State Electronics
DOI:
10.1016/j.sse.2015.11.013
Date:
December, 2015
File:
PDF, 1.69 MB
english, 2015
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