A 28 nm 2 Mbit 6 T SRAM With Highly Configurable...

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IEEE Journal of Solid-State Circuits 2015

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

Sinangil, Mahmut E., Poulton, John W., Fojtik, Matthew R., Greer III, Thomas H., Tell, Stephen G., Gotterba, Andreas J., Wang, Jesse, Golbus, Jason, Zimmer, Brian, Dally, William J., Gray, C. Thomas
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Year:
2015
Language:
english
Journal:
IEEE Journal of Solid-State Circuits
DOI:
10.1109/JSSC.2015.2498302
File:
PDF, 2.41 MB
english, 2015
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