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[IEEE 2015 Symposium on VLSI Technology - Kyoto, Japan (2015.6.16-2015.6.18)] 2015 Symposium on VLSI Technology (VLSI Technology) - Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal
Mertens, H., Ritzenthaler, R., Arimura, H., Franco, J., Sebaai, F., Hikavyy, A., Pawlak, B. J., Machkaoutsan, V., Devriendt, K., Tsvetanova, D., Milenin, A. P., Witters, L., Dangol, A., Vancoille, E.,Year:
2015
Language:
english
DOI:
10.1109/VLSIT.2015.7223654
File:
PDF, 709 KB
english, 2015