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[IEEE 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Hsinchu (2015.6.29-2015.7.2)] 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits - A sample preparation methodology to reduce sample edge unevenness and improve efficiency in delayering the 20-nm node IC chips
Feng, H., Tan, P. K., Yap, H. H., Low, G. R., He, R., Zhao, Y. Z., Liu, B., Dawood, M. K., Zhu, J., Huang, Y. M., Wang, D. D., Tan, H., Lam, J., Mai, Z. H.Year:
2015
Language:
english
DOI:
10.1109/ipfa.2015.7224432
File:
PDF, 636 KB
english, 2015