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[IEEE 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) - Macao, Macao (2016.1.25-2016.1.28)] 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) - Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques
Li, Ming-Zhong, Ieong, Chio-In, Law, Man-Kay, Mak, Pui-In, Vai, Mang-I, Pun, Sio-Hang, Martins, Rui P.Year:
2016
Language:
english
DOI:
10.1109/ASPDAC.2016.7427979
File:
PDF, 135 KB
english, 2016