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[IEEE Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings - Toronto, Ont., Canada (13-16 May 2001)] Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555) - Sp2V: accelerating post-layout spice simulation using Verilog gate-level modeling
Salimi Zebardst, A., Dara Rahmati, Z., Hamdin Yaran, B., Navabi, Z.Volume:
1
Year:
2001
Language:
english
DOI:
10.1109/ccece.2001.933692
File:
PDF, 426 KB
english, 2001