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[IEEE 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) - Ishigaki, Japan (2014.11.17-2014.11.20)] 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) - A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs
Fujiwara, Koichi, Abe, Shinya, Kawamura, Kazushi, Yanagisawa, Masao, Togawa, NozomuYear:
2014
Language:
english
DOI:
10.1109/apccas.2014.7032765
File:
PDF, 178 KB
english, 2014