Erratum: optimizing latency in Xilinx FPGA implementations...

Journal of Instrumentation 2011 / 05 Vol. 6; Iss. 5

Erratum: optimizing latency in Xilinx FPGA implementations of the GBT

Muschter, S, Baron, S, Bohm, C, Cachemiche, J.-P, Soos, C
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Volume:
6
Journal:
Journal of Instrumentation
DOI:
10.1088/1748-0221/6/05/e05001
Date:
May, 2011
File:
PDF, 43 KB
2011
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