Design Methodology for Synthesizing Resonant Clock Networks...

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2016

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage / Frequency Scaling

Ahn, Seyong, Kang, Minseok, Papaefthymiou, Marios C., Kim, Taewhan
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Year:
2016
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/tcad.2016.2543022
File:
PDF, 885 KB
english, 2016
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