[IEEE International Semiconductor Device Research Symposium, 2003 - Washington, DC, USA (Dec. 10-12, 2003)] International Semiconductor Device Research Symposium, 2003 - DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 mn LV/LP circuit design
Mitra, S., Salman, A., Ioannou, D.P., Tretz, C., loannou, D.E.Year:
2003
Language:
english
DOI:
10.1109/isdrs.2003.1272149
File:
PDF, 111 KB
english, 2003