Very Compact and Efficient 32-Bit AES Core Design Using...

Journal of Circuits System and Computers 2016 / 07 Vol. 25; Iss. 7

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

Bani-Hani, Raed, Mhaidat, Khaldoon, Harb, Salah
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Volume:
25
Language:
english
Journal:
Journal of Circuits, Systems and Computers
DOI:
10.1142/s0218126616500808
Date:
July, 2016
File:
PDF, 264 KB
english, 2016
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