SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 21 February 2016)] Design-Process-Technology Co-optimization for Manufacturability X - Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs
Capodieci, Luigi, Cain, Jason P., Liu, Hongyi, Hong, Chuyang, Han, Ting, Zhou, Jun, Chen, YijianVolume:
9781
Year:
2016
Language:
english
DOI:
10.1117/12.2219267
File:
PDF, 918 KB
english, 2016