Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism
Brandalero, Marcelo, Beck, Antonio Carlos S.Volume:
20
Language:
english
Journal:
Design Automation for Embedded Systems
DOI:
10.1007/s10617-016-9174-4
Date:
June, 2016
File:
PDF, 1.05 MB
english, 2016