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Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
Wang, Po-Hao, Tsai, Shang-Jen, Tanjung, Rizal, Lin, Tay-Jyi, Wang, Jinn-Shyan, Chen, Tien-FuVolume:
54
Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2016.01.001
Date:
June, 2016
File:
PDF, 2.23 MB
english, 2016