Cross-matching caches: Dynamic timing calibration and...

Integration, the VLSI Journal 2016 / 06 Vol. 54

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors

Wang, Po-Hao, Tsai, Shang-Jen, Tanjung, Rizal, Lin, Tay-Jyi, Wang, Jinn-Shyan, Chen, Tien-Fu
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
54
Language:
english
Journal:
Integration, the VLSI Journal
DOI:
10.1016/j.vlsi.2016.01.001
Date:
June, 2016
File:
PDF, 2.23 MB
english, 2016
Conversion to is in progress
Conversion to is failed