A 2.5-ps Bin Size and 6.7-ps Resolution FPGA...

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016

A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

Chen, Poki, Hsiao, Ya-Yun, Chung, Yi-Su, Tsai, Wei Xiang, Lin, Jhih-Min
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Year:
2016
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/TVLSI.2016.2569626
File:
PDF, 4.33 MB
english, 2016
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