Tunneling current in gate dielectric stack in sub-45...

Tunneling current in gate dielectric stack in sub-45 nanometer CMOS devices

Hitender Kumar Tyagi, B. Prasad, P. J. George
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Volume:
6
Year:
2009
Language:
english
Pages:
3
DOI:
10.1002/pssc.200982579
File:
PDF, 209 KB
english, 2009
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