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SPIE Proceedings [SPIE Microelectronic Manufacturing - Santa Clara, CA (Monday 18 September 2000)] Challenges in Process Integration and Device Technology - Yield-limiting NMOSFET gate depletion in a deep submicrometer CMOS process
Karnett, Martin P., Qian, Steven G., Mitchell, Todd, Subramaniam, Vijaya, Sur, Harlan, Haby, Bradley J., Brugge, Hunter B., Burnett, David, Kimura, Shin'ichiro, Singh, BhanwarVolume:
4181
Year:
2000
Language:
english
DOI:
10.1117/12.395729
File:
PDF, 394 KB
english, 2000