SPIE Proceedings [SPIE Microlithography 2005 - San Jose, CA...

  • Main
  • SPIE Proceedings [SPIE Microlithography...

SPIE Proceedings [SPIE Microlithography 2005 - San Jose, CA (Sunday 27 February 2005)] Design and Process Integration for Microelectronic Manufacturing III - Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Kachwala, Nishrin, Liebmann, Lars W., Iandolo, Walter, Brist, Travis, Farnbach, Rick
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
5756
Year:
2005
Language:
english
DOI:
10.1117/12.602539
File:
PDF, 589 KB
english, 2005
Conversion to is in progress
Conversion to is failed