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SPIE Proceedings [SPIE Microlithography 2005 - San Jose, CA (Sunday 27 February 2005)] Design and Process Integration for Microelectronic Manufacturing III - Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches
Kachwala, Nishrin, Liebmann, Lars W., Iandolo, Walter, Brist, Travis, Farnbach, RickVolume:
5756
Year:
2005
Language:
english
DOI:
10.1117/12.602539
File:
PDF, 589 KB
english, 2005