SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 22 February 2009)] Design for Manufacturability through Design-Process Integration III - Layout electrical cooptimization for increased tolerance to process variations
Riviere-Cazaux, Lionel, Singh, Vivek K., Rieger, Michael L., Hurat, Philippe, Kasthuri, Bala, Layton, Larry, Verghese, NishathVolume:
7275
Year:
2009
Language:
english
DOI:
10.1117/12.813969
File:
PDF, 294 KB
english, 2009