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SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 24 February 2008)] Design for Manufacturability through Design-Process Integration II - Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours
Yanagihara, Toshiaki, Singh, Vivek K., Rieger, Michael L., Hamamoto, Takeshi, Sato, Koya, Okamura, Atsushi, Matsunaga, Toshiyuki, Kobayashi, Naohiro, Maekawa, Tatsuya, Verghese, Nishath, Condella, JacVolume:
6925
Year:
2008
Language:
english
DOI:
10.1117/12.773013
File:
PDF, 457 KB
english, 2008