Integrated CPU and l2 cache voltage scaling using machine...

ACM SIGPLAN Notices 2007 / 07 Vol. 42; Iss. 7

Integrated CPU and l2 cache voltage scaling using machine learning

AbouGhazaleh, Nevine, Ferreira, Alexandre, Rusu, Cosmin, Xu, Ruibin, Liberato, Frank, Childers, Bruce, Mosse, Daniel, Melhem, Rami
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Volume:
42
Language:
english
Journal:
ACM SIGPLAN Notices
DOI:
10.1145/1273444.1254773
Date:
July, 2007
File:
PDF, 287 KB
english, 2007
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