SPIE Proceedings [SPIE Microlithography 2004 - Santa Clara, CA (Sunday 22 February 2004)] Design and Process Integration for Microelectronic Manufacturing II - Yield-enhanced layout generation by new design for manufacturability (DfM) flow
Kotani, Toshiya, Liebmann, Lars W., Tanaka, Satoshi, Nojima, Shigeki, Hashimoto, Koji, Inoue, Soichi, Mori, IchiroVolume:
5379
Year:
2004
Language:
english
DOI:
10.1117/12.536254
File:
PDF, 176 KB
english, 2004