Development of RIE-lag Reduction Technique for Si Deep...

IEEJ Transactions on Electrical and Electronic Engineering 2010 Vol. 5; Iss. 2

Development of RIE-lag Reduction Technique for Si Deep Etching Using Double Protection Layer Method

Junji Ohara, Kazushi Asami, Yukihiro Takeuchi, Kazuo Sato
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Volume:
5
Year:
2010
Language:
english
Pages:
6
DOI:
10.1002/tee.20506
File:
PDF, 406 KB
english, 2010
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