![](/img/cover-not-exists.png)
SPIE Proceedings [SPIE Microlithography 2004 - Santa Clara, CA (Sunday 22 February 2004)] Design and Process Integration for Microelectronic Manufacturing II - Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology
Honda, K., Liebmann, Lars W., Peter, K., Zhang, Y., Yu, B., Park, K., Li, Xiaolei, Michaels, K., Yamada, Shinichi, Noguchi, T.Volume:
5379
Year:
2004
Language:
english
DOI:
10.1117/12.544234
File:
PDF, 161 KB
english, 2004