A fault tolerant, area efficient architecture for Shor's...

ACM SIGARCH Computer Architecture News 2009 / 06 Vol. 37; Iss. 3

A fault tolerant, area efficient architecture for Shor's factoring algorithm

Whitney, Mark G., Isailovic, Nemanja, Patel, Yatish, Kubiatowicz, John
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Volume:
37
Language:
english
Journal:
ACM SIGARCH Computer Architecture News
DOI:
10.1145/1555815.1555802
Date:
June, 2009
File:
PDF, 468 KB
english, 2009
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