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SPIE Proceedings [SPIE Microelectronic Manufacturing - Santa Clara, CA (Monday 18 September 2000)] Challenges in Process Integration and Device Technology - MEEF measurement and model verification for 0.3-k1 lithography
Parker, Colin R., Reilly, Michael T., Burnett, David, Kimura, Shin'ichiro, Singh, BhanwarVolume:
4181
Year:
2000
Language:
english
DOI:
10.1117/12.395749
File:
PDF, 170 KB
english, 2000