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SPIE Proceedings [SPIE Electronic Imaging 2005 - San Jose, CA (Monday 17 January 2005)] Embedded Processors for Multimedia and Communications II - Breaking the I/O bottleneck for high-compute performance processing with Xtensa LX configurable and extensible processor architecture
Ezer, Gulbin A., Sudharsanan, Subramania, Bove, Jr., V. Michael, Panchanathan, SethuramanVolume:
5683
Year:
2005
Language:
english
DOI:
10.1117/12.586013
File:
PDF, 509 KB
english, 2005