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SPIE Proceedings [SPIE Microelectronic Manufacturing - Santa Clara, CA (Monday 18 September 2000)] Challenges in Process Integration and Device Technology - Investigations on the impacts of misalignment in the integration of 0.18-μ multilevel interconnect
Tang, Teck Jung, Tan, Juan Boon, Marokkey, Sajan R., Lee, Tae J., Cuthbertson, Alan, Burnett, David, Kimura, Shin'ichiro, Singh, BhanwarVolume:
4181
Year:
2000
Language:
english
DOI:
10.1117/12.395716
File:
PDF, 630 KB
english, 2000