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SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, USA (Sunday 22 February 2009)] Design for Manufacturability through Design-Process Integration III - Enhanced layout optimization of sub-45nm standard: memory cells and its effects
Paek, Seung Weon, Singh, Vivek K., Rieger, Michael L., Jang, Dae Hyun, Park, Joo Hyun, Ha, Naya, Kim, Byung-Moo, Won, Hyo Sig, Choi, Kyu-Myung, Lin, Kuang-Kuo, Klaver, Simon, Malik, Shobhit, OostindieVolume:
7275
Year:
2009
Language:
english
DOI:
10.1117/12.815413
File:
PDF, 652 KB
english, 2009