SPIE Proceedings [SPIE Microlithography 2004 - Santa Clara, CA (Sunday 22 February 2004)] Design and Process Integration for Microelectronic Manufacturing II - Optimization of interconnection layout for multitransistor cell shrinkability
Banachowicz, Bartosz, Liebmann, Lars W., Pohland, Oliver, Balasinski, ArturVolume:
5379
Year:
2004
Language:
english
DOI:
10.1117/12.535975
File:
PDF, 87 KB
english, 2004